Jnr Analogue Design Engineer


Premium Job From Enigma People Solutions Ltd

Recruiter

Enigma People Solutions Ltd

Listed on

17th April 2015

Location

Edinburgh

Salary/Rate

£24000 - £30000

Salary Notes

up to £30,000

Type

Permanent

Start Date

May/June 2015

This job has now expired please search on the home page to find live IT Jobs.

Enigma People Solutions is recruiting an Analogue Design Engineer for a long term client based in Edinburgh. This is an exciting opportunity to join a dynamic team focussed on the rapidly expanding photonics market, working on State-of-the-Art Time of Flight ranging solutions employing our client’s industry leading SPAD (Single Photon Avalanche Diode) technology.

The role is within the Edinburgh Analogue Design Team, bringing with it challenges in the specification, design, modelling and implementation of analogue blocks. Regular interaction with engineers in other disciplines is essential for product development: work alongside digital design, analogue/digital back end, architecture, validation, characterisation, optics, mechanical design, failure analysis, test), ensures that designers builds knowledge of the full product development.

Key skills

         •       Bachelor’s or Masters degree in Electronic Engineering or a related degree.

         •       Analogue Design and simulation

         •       Analogue Subsystems

         •       Analogue Behavioural Simulation and modelling techniques

         •       Mixed signal simulation

         •       Layout

Additional Skills

         •       Cadence tools for schematic capture and layout

         •       Eldo

         •       Fastpice simulators

         •       Bench Characterisation / silicon debug

The successful candidate will have a solid background in analogue design, with the ability to demonstrate a clear understanding of the fundamentals. They will be responsible for the schematic capture, layout / layout supervision, extraction and simulation of analogue IP and subsequently for its integration into the top level of the design.

It is desirable the candidate will have experience designing CMOS IP blocks such as LDO regulators, charge pumps, oscillators, PLL, or DAC/ADC. It would be advantageous if the candidate can demonstrate some prior knowledge of Time of Flight or CMOS imaging.

Experience ranging from graduate level upwards will be considered. The candidate must be capable of rapidly assembling knowledge in new environments, understanding complex issues and deriving innovative solutions to improve design, verification and flow. Understanding design interactions at system level will be critical to the definition of quality cell level specifications.

The candidate must be team focussed and highly motivated. Collaboration with colleagues locally and in the wider design/engineering community across the Imaging Division is a key factor for success. Experience leading the development of analogue sub-systems would be advantageous. Strong communication skills are mandatory.

You are currently using an outdated browser.

Please consider using a modern browser such as one listed below: