Digital Verification Engineer - UVM

Working for an exciting fabless semiconductor company, the successful digital verification engineer will work in a challenging technical environment on the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market.

The candidate will be involved in the verification of the digital processing functions of the ASIC in close collaboration with the mixed-signal and digital IC design engineers.

Qualification and Experience 

• You have a MSc or PhD in Electrical Engineering or equivalent and 3+ years of hands-on experience in digital IC verification
• You have solid knowledge of a digital hardware description languages (VHDL or Verilog) and scripting languages (TCL, Perl, Python)
• You have solid knowledge of System Verilog and UVM methodology & processes
• Experience in formal verification & gate-level simulations are a plus
• A previous experience in verification of digital functions for Mixed-Signal ICs such as A/D Converters, D/A Converters, and/or RF transceivers is a plus
• Good knowledge of Cadence or Synopsys RTL design tools
• A previous experience with FPGA is a plus
• You are a team player with a critical attitude and sense of initiative
• You communicate fluently in English (oral and written)